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Readers acquire understanding of why leakage power components are becoming increasingly relevant in CMOS systems that use nanometer scale MOS devices. Leakage current sources at the MOS device level including sub-threshold and different types of tunneling are discussed in detail. The book will cover in detail promising solutions at the device, circuit, and architecture levels of abstraction. Since manifestation of these MOS device leakage components at the full chip level depends considerably on several aspects including the nature of the circuit block, its state, its application workload, and Process/Voltage/Temperature conditions, the sensitivity of the various MOS leakage sources to these conditions are explained from the first principles. Also treated are the resulting effects so the reader understands the effectiveness of leakage power reduction solutions under these different conditions. With case studies supplying real-world examples that reap the benefits of leakage power reduction solutions, the book highlights different device design choices that exist to mitigate increases in the leakage components as technology scales.
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